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data sheet ics8530fy-01 revision g november 15, 201 2 1 ?2012 integrated device technology, inc. low skew, 1-to16, differential-to-3.3v lvpecl fanout buffer ICS8530-01 general description the ICS8530-01 is a lo w skew, 1-to-16 differential-to-3.3v lvpecl fanout buffer. the clk, nclk pair can accept most standard differential input levels. the high gain differential amplifier accepts peak-to-peak input voltages as small as 150mv as long as the common mode voltage is within the specified minimum and maximum range. guaranteed output and pa rt-to-part skew characteristics make the ICS8530-01 ideal for those clock distribution applications demanding well defined performance and repeatability. features ? sixteen differential 3.3v lvpecl outputs ? clk, nclk input pair ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? maximum output frequency: 500mhz ? translates any single-ended input signal to 3.3v lvpecl levels with a resistor bias on nclk input ? output skew: 75ps (maximum) ? part-to-part skew: 305ps (maximum) ? additive phase jitter, rms: 0.03ps (typical) ? full 3.3v supply voltage ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 v cco q11 n q11 q10 n q10 v ee q9 nq9 q8 nq8 v cco v cc clk v cc o nq 0 q0 nq 1 q1 v ee nq 2 q2 nq 3 q3 v cc o v cc v cco q7 nq7 q6 nq6 v ee q5 nq5 q4 nq4 v cco 48 47 46 45 44 43 42 41 40 39 38 37 v cco nq1 2 q12 nq1 3 q13 v ee nq1 4 q14 nq1 5 q15 v cco ncl k pulldown pullup q15 nq15 clk nclk q14 q13 q12 nq14 nq13 nq12 q11 nq11 q10 q9 q8 nq10 nq9 nq8 q0 nq0 q1 q2 q3 nq1 nq2 nq3 q4 nq4 q5 q6 q7 nq5 nq6 nq7 block diagram pin assignment ICS8530-01 48-lead lqfp 7mm x 7mm x 1.4mm package body y package top view
ics8530fy-01 revision g november 15, 201 2 2 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 11, 14, 24, 25, 35, 38, 48 v cco power output supply pins. 2, 3 q11, nq11 output differential output pair. lvpecl interface levels. 4, 5 q10, nq10 output differential output pair. lvpecl interface levels. 6, 19, 30, 43 v ee power negative supply pins. 7, 8 q9, nq9 output differential output pair. lvpecl interface levels. 9, 10 q8, nq8 output differential output pair. lvpecl interface levels. 12, 13 v cc power power supply pins. 15, 16 q7, nq7 output differential output pair. lvpecl interface levels. 17, 18 q6, nq6 output differential output pair. lvpecl interface levels. 20, 21 q5, nq5 output differential output pair. lvpecl interface levels. 22, 23 q4, nq4 output differential output pair. lvpecl interface levels. 26, 27 q3, nq3 output differential output pair. lvpecl interface levels. 28, 29 q2, nq2 output differential output pair. lvpecl interface levels. 31, 32 q1, nq1 output differential output pair. lvpecl interface levels. 33, 34 q0, nq0 output differential output pair. lvpecl interface levels. 36 clk input pulldown non-inverting differential clock input. 37 nclk input pullup inverting differential clock input. 39, 40 q15, nq15 output differential output pair. lvpecl interface levels. 41, 42 q14, nq14 output differential output pair. lvpecl interface levels. 44, 45 q13, nq13 output differential output pair. lvpecl interface levels. 46, 47 q12, nq12 output differential output pair. lvpecl interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 3pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics8530fy-01 revision g november 15, 201 2 3 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer function table table 3. clock input function table note 1: refer to the applic ation information section, wiring the differential input to accept single-ended levels. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operat ion of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c inputs outputs input to output mode polarity clk nclk q[0:15] nq[0:15] 0 1 low high differential to differential non-inverting 1 0 high low differential to differential non-inverting 0 biased; note 1 low high single-e nded to differential non-inverting 1 biased; note 1 high low single-ended to differential non-inverting biased; note 1 0 high low single-ended to differential inverting biased; note 1 1 low high single-ended to differential inverting item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current surge current 50ma 100ma package thermal impedance, ? ja 53.9c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v cc power supply voltage 3.135 3.3 3.465 v v cco output supply voltage 3.135 3.3 3.465 v i ee power supply current 146 ma
ics8530fy-01 revision g november 15, 201 2 4 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer table 4b. differential input dc characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . table 4c. lvpecl dc ch aracteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c note 1: outputs terminated with 50 ? to v cco ? 2v. ac electrical characteristics table 5. ac electrical characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature range, which is established when de vice is mounted in a test socket with maintained transverse airflow great er than 500 lfpm. device will meet specifications after therma l equilibrium has been reached under these conditions. note all parameters measured at 250mhz unless noted otherwise. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: this parameter is defined in accordance with jedec standard 65. note 3: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential cross points. note 4: defined as skew between outputs on different devices oper ating at the same supply voltage, same temperature, same frequ ency and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cros s points. symbol parameter test conditio ns minimum typical maximum units i ih input high current clk v in = v cc = 3.465v 150 a nclk v in = v cc = 3.465v 5 a i il input low current clk v in = 0v, v cc = 3.465v -5 a nclk v in = 0v, v cc = 3.465v -150 a v pp peak-to-peak input voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 v ee + 0.5 v cc ? 0.85 v symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cco ? 1.4 v cco ? 0.9 v v ol output low voltage; note 1 v cco ? 2.0 v cco ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typic al maximum units f max output frequency 500 mhz t jit buffer additive phase jitter, rms; refer to additive phase jitter section 106.25mhz, integration range: 12khz ? 20mhz 0.03 ps t pd propagation delay; note 1 ? ? 500mhz 1 2 ns t sk(o) output skew; note 2, 3 75 ps t sk(pp) part-to-part skew ; note 2, 4 148 305 ps t r / t f output rise/ fall time 20% to 80% @ 50mhz 300 750 ps odc output duty cycle 47 50 53 %
ics8530fy-01 revision g november 15, 201 2 5 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specifi ed, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the fr equency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is ma thematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than th e noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. additive phase jitter @ 106.25mhz 12khz to 20mhz = 0.03ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
ics8530fy-01 revision g november 15, 201 2 6 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer parameter measurem ent information 3.3v output load ac test circuit output skew output duty cycle/pulse width/period differential input level part-to-part skew propagation delay scope qx nqx v ee -1.3v0.165v v cc, v cco 2v nqx qx nqy qy t sk(o) t pw t period t pw t period odc = x 100% q[0:15] nq[0:15] nclk clk v cc v ee v cmr cross points v pp t sk(pp) p art 1 p art 2 nqx qy qx nqy t pd q[0:15] nq[0:15] clk nclk
ics8530fy-01 revision g november 15, 201 2 7 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer parameter measurement information, continued output rise/fall time applications information recommendations for unused output pins outputs: lvpecl outputs the unused lvpecl output pair can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. 20% 80% 80% 20% t r t f v swing q[0:15] nq[0:15]
ics8530fy-01 revision g november 15, 201 2 8 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration r equires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefi ts of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifie s a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than vcc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a di fferential input to accept single-ended levels
ics8530fy-01 revision g november 15, 201 2 9 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer differential clock input interface the clk /nclk accepts lvds, l vpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the clk/nclk input driven by th e most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example in figure 2a, the input termination applies for idt?s lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. clk/nclk input driven by an idt lvhstl driver figure 2c. clk/nclk input driven by a 3.3v lvpecl driver figure 2e. clk/nclk input driven by a 3.3v hcsl driver figure 2b. clk/nclk input driven by a 3.3v lvpecl driver figure 2d. clk/nclk input driven by a 3.3v lvds driver figure 2f. clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differenti al input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 *r4 33 clk nclk 3.3v 3.3v zo = 50 zo = 50 differential input r1 50 r2 50 *optional ? r3 and r4 can be 0 zo = 50 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 zo = 50 clk nclk differential input sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ics8530fy-01 revision g november 15, 201 2 10 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low impedance follower outputs that generate ecl/lvpecl compatible ou tputs. therefor e, terminating resistors (dc current pa th to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommend ed that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 3a. 3.3v lvpecl output termination figure 3b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 r2 50 rtt z o = 50 z o = 50 + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 r2 84 3.3v r3 125 r4 125 z o = 50 z o = 50 lvpecl input 3.3v 3.3v + _
ics8530fy-01 revision g november 15, 201 2 11 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer power considerations this section provides information on power dissi pation and junction temperature for the ICS8530-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS8530-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 146ma = 505.89mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 16 * 30mw = 480mw total power_ max (3.465v, with all outputs switching) = 505.89mw + 480mw = 985.89mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and b ond pad and it directly affects the reliabil ity of the device. the maximum recommended junction temperature is 125c. limiting th e internal transistor junction temperature, tj, to 125c ensu res that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, th e appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 53.9c/w per table 6 below. therefore, tj for an ambi ent temperature of 70c with all outputs switching is: 70c + 0.986w * 53.9c/w = 123.1c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 48 lead lqfp, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 53.9c/w 47.7c/w 45.0c/w
ics8530fy-01 revision g november 15, 201 2 12 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer 3. calculations and equations. the purpose of this section is to calculate the power dissipa tion for the lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 4. figure 4. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max ? v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v coc_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l] * (v cco_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cco v cco - 2v q1 rl 50
ics8530fy-01 revision g november 15, 201 2 13 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer reliability information table 7. ? ja vs. air flow table for a 48 lead lqfp transistor count the transistor count for ICS8530-01 is: 955 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 53.9c/w 47.7c/w 45.0c/w
ics8530fy-01 revision g november 15, 201 2 14 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer package outline and package dimensions package outline - y suffix for 48 lead lqfp table 8. package dimensions for 48 lead lqfp reference document: jedec publication 95, ms-026 jedec variation: bcb - hd all dimensions in millimeters symbol minimum nominal maximum n 48 a 1.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.50 ref. e 0.5 basic l 0.45 0.60 0.75 ? 0 7 ccc 0.08
ics8530fy-01 revision g november 15, 201 2 15 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer table 9. ordering information note: "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8530fy-01lf ics8530f01lf lead-free, 48 lead lqfp tray 0 ? c to 70 ? c 8530fy-01lft ics8530f01lf lead-free, 48 lead lqfp 1000 tape & reel 0 ? c to 70 ? c while the information presented herein has been checked for both ac curacy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, wh ich would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial applications. any other applicat ions, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics8530fy-01 revision g november 15, 201 2 16 ?2012 integrated device technology, inc. ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer revision history sheet rev table page description of change date b 5-6 7 updated figures. added termination for lvpecl outputs section. 05/28/02 b 2 5 pin description table - v cc description changed to "core supply pin" from "positive supply pin". output load test circuit diagram - corrected v ee equation to read, v ee = -1.3v 0.165v from v ee = -1.3v 0.135v. 10/02/02 c t2 t4a 2 3 3 6 7 8 pin characteristics table - changed c in 4pf max. to 4pf typical. updated amr output rating. power supply table - changed i ee max. from 120ma to 140ma. updated single ended signal driv ing differential input diagram. added differential clock input interface section. power considerations, changed i ee to 140ma to reflect the power supply table and recalculated the equations. update format throughout the data sheet. 4/7/04 c t9 12 added "lead-free" marking to ordering information table. 6/29/04 d t5 1 4 5 features section - added additive phase jitter bullet. ac characteristics table - added tjit row. added additive phase jitter section. 2/28/05 e t4c t9 3 7 14 lvpecl dc characteristics - changed v swing (max) limit from 850mv to 1.0v. corrected v oh (max) limit from v cco - 1.0v to v cco - 0.9v. added recommendations for unused output pins. ordering information table - added lead-free note. 5/19/06 f 1 2 t4a t4b t5 t9 2 2 3 3 4 4 8 9 10 11 13 15 pin description table - change v cc description from ?core? to ?power?. pin characteristics table - change c in from 4pf typical to 3pf typical. absolute maximum rating - updated thermal impedance. power supply dc characteristics table - change i ee from 140ma max to 146ma max. differential dc characteristics table - updated notes. ac characteristics table - changed part-to- part skew spec and output rise/fall time spec. updated wiring the differential input to accept single-ended levels. updated differential clock input interface. updated figures 3a and 3b. updated power considerations to reflect power supply table, and updated thermal resistance table. updated thermal table and transistor count. ordering information table - deleted ?ics? prefix in part/order column. changed revision from ?d? to ?f?. converted datasheet format. 11/18/10 g t5 4 ac characteristics table - corrected typical pa rt-to-part skew spec from 150 to 148ps. 11/30/10 g t9 15 removed leaded orderable parts from ordering information table 11/15/12
ICS8530-01 data sheet low skew, 1-to-16, differential-to-3.3v lvpecl fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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